Vladimir Drach


The border traps, in particular slow border traps, are being investigated in metal-oxide-semiconductor structures, utilizing n-channel MOSFET as a test sample. The industrial process technology of test samples manufacturing is described. The automated experimental setup is discussed, the implementation of the experimental setup had made it possible to complete the entire set of measurements. The schematic diagram of automated experimental setup is shown. The charging time characteristic of the ID-VG shift reveals that the charging process is a direct tunnelling process and highly bias dependent.

Ключевые слова

MOSFET; gate oxide; border traps; direct tunnelling

Полный текст:

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(c) 2016 International Journal of Advanced Studies

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ISSN 2328-1391 (print), ISSN 2227-930X (online)